This invention relates to an improved architecture for a random access memory.
In the area of digital signal processing, random access memories (RAMs) have been used for years as a means of storing digital data. A typical integrated circuit RAM contains a memory array, circuitry--typically row and column decoders--which addresses selected memory elements, or locations, within that array, and input/output circuitry. The memory array contains a plurality of intersecting row and column lines arranged in a grid. One memory element, capable of holding, for example, one bit of information, is provided at the point of intersection of every row and column line.
Memory elements can be classified as either static or dynamic. Dynamic memory elements are those in which the value of any data stored therein slowly decays with time. To preserve the stored data for an indefinite time, each dynamic memory element must be periodically read and its contents written back with the same data. This process is known as refresh. Static memory elements, on the other hand, are those capable of storing data for an indefinite period of time without refresh.
To access information stored within a RAM, a portion of an address supplied to the memory is applied to the row decoder. In response to this portion, the row decoder selectively energizes a particular one of the plurality of row (or word) lines. Each bit in a resulting accessed row is then read onto a respective column (or bit) line. A sense amplifier connected to each bit line detects the level of the bit present on that line, and amplifies it to a higher level. In the case of a RAM comprised of dynamic memory elements, the resulting amplified bit is then applied to the same bit line in order to facilitate refresh. In response to the remainder of the address, the column decoder in conjunction with the input/output circuitry applies the amplified bit present on a selected one of the bit lines to the memory output.
Over the past few years, a variety of RAM technologies have been developed, e.g., RAMs containing bipolar memory elements and those containing metal oxide semiconductor (MOS) elements. The former have significantly faster access speeds than the latter. However, bipolar based memories consume a relatively large amount of power, contain relatively few locations per chip, and are expensive. Advantageously, MOS RAMs not only consume far less power, but also can be provided at a much lower price than bipolar. Moreover, recent developments in the design of digital integrated circuits have led to significant decreases in the physical size of individual MOS memory elements, and correspondingly have provided significant increases in the storage capacity of individual MOS RAM chips. Consequently, the number of MOS memory chips required to implement a memory system of given storage capacity, i.e., the "chip count," has significantly decreased.
However, various physical constraints on the design of MOS RAMs, for example, substantial internal capacitances and limited chip pinout, have generally prevented the bandwidth of a MOS RAM, i.e., the amount of data that can be transferred into or out of the memory chip per unit time, from being increased. Consequently, decreasing the chip count of an MOS based memory system of given storage capacity causes a reduction in the overall bandwidth. Thus, in those applications where the operating speed of the digital system is primarily determined by memory bandwidth, e.g., video frame stores, use of relatively inexpensive, high capacity MOS RAMs is no longer being favored over more expensive, less dense RAMs.
Various approaches aimed at increasing the bandwidth of a MOS RAM have been disclosed in the art. In particular, C. J. Fassbender in U.S. Pat. No. 4,106,109 issued Aug. 8, 1978, teaches that the access rate of a multi-array MOS RAM can be increased by storing the bit produced by each array during a memory read operation in a separate register, positioned external to the memory arrays, prior to applying these bits to the output circuitry. Disadvantageously, this arrangement only increases access speed during a memory read operation and requires a significant amount of area on the integrated circuit for routing the leads connecting the register to the existing memory circuitry. Alternatively, Kitagawa et al, in U.S. Pat. No. 4,144,590, issued Mar. 13, 1979, teach that access speed can be increased by amplifying the output signal of each sense amplifier prior to applying it to a respective bit line. However, while this arrangement requires a small amount of additional circuitry, the increase in access speed produced thereby is insufficient to overcome the bandwidth limitation in a typical high-capacity, low chip-count MOS based memory system.